This invention relates to electrical interconnection of integrated circuit chips and, particularly, to interconnection of stacked die.
A typical semiconductor die has a front (“active”) side, in which the integrated circuitry is formed, a back side, and sidewalls. The sidewalls meet the front side at front edges and the back side at back edges. Semiconductor die typically are provided with interconnect pads (die pads) located at the front side for electrical interconnection of the circuitry on the die with other circuitry in the device in which the die is deployed. Some die as provided have die pads on the front side along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows at the front side near the center of the die, and these may be referred to as central pad die. The die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the margins of the die. A die margin along which interconnect pads are arranged may be referred to as an “interconnect margin”, the adjacent front die edge may be referred to as an “interconnectedge”, and a die sidewall adjacent an interconnect die edge may be referred to as an “interconnect sidewall”.
Semiconductor die may be electrically connected with other circuitry, for example in a printed circuit board, a package substrate or leadframe, or another die, by any of several means. Connection may be made, for example, by wire bonds, or by flip chip interconnects, or by tab interconnects.
A number of approaches have been proposed for increasing the density of active semiconductor circuitry in integrated circuit chip packages, while minimizing package size (package footprint, package thickness). In one approach to making a high density package having a smaller footprint, two or more semiconductor die, of the same or different functionality, are stacked one over another and mounted on a package substrate.
Wire bond interconnect requires both vertical clearance over the die surface at the front side margin, to accommodate the wire loop height, and horizontal clearance outside the die footprint, to accommodate the wire span. If the vertical clearance is insufficient, overlying features may interfere with or introduce electrical shorting to the wire loops. And, in practice, the lower interconnect pad or bond site must be located some distance away from the sidewall of the overlying die, so that the wire bonding tool does not impact the die edge during the bonding process, and so that the wire bond does not contact the front edge of the die.
Electrical interconnection of stacked semiconductor die presents a number of challenges. For instance, two or more die in a stack may be mounted on a substrate with their front sides facing away from the substrate, and connected by wire bonds die-to-substrate or die-to-die. Die-to-die wire bond interconnect may be made where an upper die is dimensioned or located so that the upper die does not overlie the margin of the lower die to which it is connected, and so that sufficient horizontal clearance is provided for the wire span. This condition may pertain, for example, where the footprint of the upper die is sufficiently narrower than the lower die; or, for example, where the upper die is arranged so that the footprint of the upper die is offset in relation to the margin of the lower die. Alternatively, the die in the stack may be indirectly interconnected by connecting them to a common substrate on which the stack is mounted. Where a lower die in a stack is wire bonded die-to-substrate, and where the footprint of an upper die overlies the margin of the lower die, a spacer may be interposed to provide sufficient vertical clearance between the lower and the upper die to accommodate the wire loops over the lower die. The spacer adds to the thickness of the stack and, consequently, of the package. Moreover, in such a configuration the wire bond die-to-substrate connection of the lower die must be completed before the spacer and the upper die are stacked over it; that is, the die must be stacked in situ on the substrate and the die must be stacked and connected serially.
Die pads in processed semiconductor wafers as provided, or in singulated die, may not be arranged along one die edge, or along two adjacent die edges. The pads may be arranged in one or two rows near a centerline of the die, for example; or, if arranged along die edges, they may be arranged along two opposite die edges or along all four die edges, for example. Or, whatever the arrangement of pads on the wafer or on the die as provided, they may not be arranged in a suitable manner for a given end use; they may be located in an unsuitable sequence, or at an unsuitable pitch, for example). In such instances, the wafer or die as provided may if desired be further processed to reroute the original pads to new pad positions along one die edge or along two die edges, prior to mounting the die in stacks for interconnection according to the invention.
Also typically, a wafer as provided, or a singulated die, may optionally have a dielectric layer (such as glass, silicon nitride, polyimide, or a benzcyclobutene (BCB) polymer, for example) formed over the integrated circuitry except over the original die pads. This may suffice to provide electrical insulation of circuitry in the active side of the die from electrical conductors (including, for example, a first layer of rerouting circuitry) that may be formed over the front side of the die or wafer. Optionally a dielectric layer (such as glass, silicon nitride, polyimide, or a benzcyclobutene (BCB) polymer, for example) may additionally be formed over the rerouting circuitry except over the new (rerouted) interconnect pads. In such instances additional insulation between the front side of a die and the back side of a die stacked over it may be unnecessary.